A signaling technique referred to as “non-return-to-zero” or “NRZ” signaling concatenates adjacent bits without inserting a “return-to-zero” (RZ) or other transition between the bits. In NRZ signaling transitions occur only when the data value changes, for example from a binary “0” to a binary “1.” Therefore, not having a transition with each bit for a sampling reference, the NRZ signal receiver must locally generate a sampling clock, and can only use data transitions for synchronization. NRZ signaling, however, requires for any given bit rate approximately one-half the bandwidth required by RZ signaling.
Conventional techniques exist for an NRZ receiver to locally generate a sampling clock synchronized in frequency and phase to the data in the NRZ signal. One such technique generates a sampling clock at a frequency equal to the bit rate of the NRZ signal, for example using a phase-lock-loop (PLL) fed by a local reference oscillator. In one such technique the NRZ signal is supplied to the signal input of a sampler that, in turn, is triggered by the locally generated sampling clock. However, since the locally generated sampling clock is at the NRZ signal bit rate, when the latter is increased to a high rate the former must be increased in turn. Generation of high frequency sampling clocks can incur costs in terms of power consumption and in circuit considerations such as signal path transmission line quality, requirements for noise isolation, in addition to reduced fabrication tolerance. Further, NRZ data can be communicated in a burst mode, requiring fast lock time, without benefit of a preamble.
Another conventional technique for recovering NRZ data entails generating a local clock having a frequency that is a fraction, i.e., 1/N (N generally being an integer) of the bit rate and, in combination, generating an N-phase sampling clock based on that 1/N rate clock. The N-phase sampling clock can trigger N samplers receiving the NRZ signal. However, conventional generation of N-phase sampling clocks generally requires a significant number of circuit blocks or cells, including voltage-controlled delay elements, multiplexers, and logic, with associated interconnects. Various ones of the circuit blocks or cells, in particular the voltage controlled delay elements, are connected in cascade, with tap-offs placed at various ones of the interconnects. N of the tap-off are, in turn, the N phases of the sampling clock. In this conventional generation of an N-phase sampling there are differences in configuration among the voltage controlled delay elements, as well in the loading at the outputs of different ones of the elements. However, since the relative delay among the voltage controlled delay elements establishes the different phases of the N-phase sampling clock, such differences in their configuration and output loading can result in non-uniform phase differences between the N clock phases. The non-uniform phase difference can, in turn, result in a timing offset between the ideal sampling instant of the NRZ signal and the actual sampling instant. Compensation circuitry can be included, but this can itself introduce complications in circuit structure. Also, since the compensation circuitry and the voltage controlled delay elements generally have different structure, process variances can produce non-uniform shifts in delay, which can result in the compensation circuitry introducing the very problem it was intended to correct.
The objective is to reduce power consumption further, and one way would be to increase the data rate by sampling four parallel data in a single clock cycle with multiple phases. This has been done before, but required significantly more than four multiplexers.